Demodulation method

ABSTRACT

A demodulation method for establishing clock synchronization within a short period of time from a received signal modulated by π/4-shift QPSK modulation that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, and demodulating said received signal comprises a step of establishing synchronization from said received signal based on the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, and demodulating said received signal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a demodulation method wherein clock synchronization is established from a burst signal modulated by means of the π/4-shift QPSK (Quadrature Phase Shift Keying) modulation scheme, for example, and to a synchronization establishment apparatus, modem or base station, and particularly to a technique for establishing synchronization in a short period of time.

[0003] 2. Description of the Prior Art:

[0004] In a wireless communications system wherein wireless communication is performed in a burst manner, a wireless transmitter wirelessly transmits a burst signal modulated by a modulator, and at the time that a wireless receiver begins the receipt of the burst signal, the establishment of clock synchronization from the burst signal is performed by a demodulator. In addition, in such a wireless communications system, various modulation schemes and demodulation schemes are used, for example, π/4-shift QPSK.

[0005]FIG. 11 shows one example of the structure of a burst signal.

[0006] As shown in this figure, the various burst slots contained within a burst signal consist of, in order from the beginning, a preamble pattern (PR) which is a pattern for establishing synchronization, a unique word (UW) which is an identification pattern for determining the base position of the burst, DATA which is the body of communications data, and guard bits (GB) which prevent the overlapping of bursts by providing buffer timing between slots.

[0007] When communications is performed in bursts, the receiver refers to the preamble pattern at the start of receiving the respective bursts, and establishes the synchronization of its own clock. When a burst signal having a frame format as shown in FIG. 11 above is used, it is preferable to establish synchronization prior to the unique word, for example.

[0008] In addition, FIG. 12 shows one example of a demodulation circuit implemented in a wireless receiver that establishes clock synchronization as described above. In this demodulation circuit, clock synchronization is established by means of feedback control as a typical method. In addition, the example shown in this figure illustrates the case in which demodulation is performed by the delay detection system wherein π/4-shift QPSK is used as the modulation scheme.

[0009] Specifically, in the demodulation circuit illustrated in the figure, a (π/4-shift QPSK) burst signal received by a wireless receiver is converted from an analog signal to a digital signal by means of an A/D converter 61, demodulated into an I component (in-phase component) and Q component (quadrature component) by a demodulator 62, and then the I component and Q component are filtered by filter 63 and filter 64, respectively

[0010] The I component and Q component output from the two filters 63 and 64 are input to a (delayed) detector 65 and also input to a clock phase detection circuit 66. Moreover, in the detector 65, the input I component and Q component are demodulated by delayed detection to generate demodulated data. In addition, a parallel/serial converter 68 converts the demodulated data of the I component and Q component output from the detector 65 from parallel data to serial data. In addition, the clock phase detection circuit 66 detects the phase of the clock from the input I component and Q component, and a clock regeneration circuit 67 generates a synchronization clock based on the results of this detection, while feedback control of the aforementioned AID converter 61, filters 63 and 64, and detector 65 is performed.

[0011] As an example of the prior art of π/4-shift QPSK synchronization detection circuits, we shall describe the “Digital Demodulation Circuit, Maximum Value Detection Circuit and Receiver” recited in the publication of unexamined Japanese patent application JP-A-9-266499.

[0012] This example of prior art relates to a Personal Handy phone System (PHS) or other mobile communications system, and with the object of providing a digital demodulator having a synchronization detection circuit that enables high-speed operation and that can be implemented in a more compact manner or in ICs, and relates to technology for eliminating frequency errors and phase errors between the transmitter and receiver.

[0013] Specifically, in this prior-art example, a preamble pattern consisting of a repeated pattern of “1001” is used, and by detecting the frequency difference during the period of this preamble pattern, and by forming a frequency difference compensation signal based on a phase change pattern of instantaneous phase signals during this preamble pattern, it is intended to enlarge the permissible range of phase noise over which the phase difference between the carrier signals can be correctly detected.

[0014] In addition, in this prior-art example, a carrier generator compares the phase of the carrier signal it generates itself against the phase of the carrier signal of the received signal, to detect the phase error, and thus the establishment of synchronization is performed by correcting this phase error. In addition, in this prior-art example, the phase of the π/4-shift QPSK received signal is shifted backwards by π/4 and processing is performed in a manner corresponding to QPSK. In this case, the preamble pattern becomes a waveform wherein a phase change of π is repeated every symbol, so it can be treated as a Binary Phase Shift Keying (BPSK) signal, and thus it is resistant to erroneous detection due to phase noise and high-precision phase detection is possible.

[0015] However, in the prior-art demodulation circuit shown in FIG. 12 above, in order to establish clock synchronization based on the preamble pattern, with the performance of a typical receiver, there is a difficulty in that a reception period as long as approximately 100 symbols from the start of reception of the burst signal is required

[0016] With reference to FIG. 13, we shall describe in detail the problems that occur due to the aforementioned difficulty.

[0017]FIG. 13(a) shows an example of the structure of a burst signal in the case wherein, in order to handle the long period until the establishment of the clock of approximately 100 symbols, a preamble pattern having a length (period) equivalent to 100 symbols or longer is provided. However, in this case, since the length (period) of the preamble pattern becomes a large fraction of the length (period) of the entire burst slot, there is a problem in that this preamble pattern period becomes wasted time in data communications, thus decreasing the data communications (transmission) rate.

[0018] In addition, FIG. 13(b) shows an example of the structure of a burst signal in the case wherein the length (period) of the preamble pattern is not as long as that shown in FIG. 13(a). In this case, there is a possibility that the received signal cannot be demodulated correctly during the period of roughly 100 symbols from the start of reception, so there is a possibility that at the time of reception of the first burst, the unique word and data periods also cannot be demodulated normally. For this reason, there is the problem in that it will be assumed that the data received during the receipt of the first burst cannot be received normally and thus this data received in the first burst will be discarded. In addition, there is also the problem in that the timing of synchronization established at the time of receipt of the first burst must be stored for use at the time of receipt of the second and subsequent bursts.

[0019] The present invention came about in order to solve the aforementioned problems with the prior art and has as its object to provide a demodulation method wherein, at the time of the establishment of clock synchronization based on a burst pattern contained at the front of a (π/4-shift QPSK) burst signal, synchronization can be established in a short period of time, along with a synchronization establishment apparatus, modem or base station.

SUMMARY OF THE INVENTION

[0020] To attain the above object, the demodulation method according to the present invention comprises establishing synchronization from a received signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, and demodulating said received signal, and specifically establishing synchronization from said received signal based on the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, and demodulating said received signal.

[0021] Accordingly, by establishing the synchronization (e.g., clock synchronization) based on the timing at which the amplitude difference of the synchronization establishment signal (e.g., a preamble pattern) periodically alternates between positive and negative, it is possible to establish synchronization in a short period of time. Thereby, it is possible to make the length (period) of the preamble pattern relatively short and increase the data transmission rate. In addition, even when a preamble pattern of a short length (period) is used, synchronization is established within the period of the preamble pattern, so it is possible for the received data in the first burst reception to be received correctly and reliably.

[0022] In addition, in the demodulation method according to the present invention, at the time of performing demodulation as described above, from a plurality of received signals, synchronization is established for each received signal and each of said received signals is demodulated.

[0023] As described above, with the present invention, synchronization can be established in a short period of time, so even in the above case in which a plurality of received signals containing synchronization establishment signals are received at nearly the same timing, it is possible to establish synchronization with each of this plurality of received signals in a short period of time, and thus it is possible to establish synchronization in a short period of time with the entire plurality of received signals.

[0024] In addition, with the present invention, when the same technical idea as that of the aforementioned demodulation method according to the present invention is applied to a synchronization establishment apparatus, modem and base station, the establishment of synchronization from received signals was achieved in a short period of time in the same manner as above.

[0025] To wit, in a synchronization establishment apparatus according to the present invention, at the time of establishing synchronization from a received signal containing a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, the positive/negative change timing detection means detects the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, and synchronization is established from said received signal based on the timing detected by the synchronization establishment means.

[0026] In addition, the modem according to the present invention, in the following manner, modulates transmitted signals, and also establishes synchronization from a received signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, demodulates said received signal. To wit, the modulating means modulates transmitted signals, the positive/negative change timing detection means detects the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, the synchronization establishment means establishes synchronization from said received signal based on the timing detected by the synchronization establishment means, and the demodulation means demodulates said received signal according to the synchronization timing established by the demodulation means.

[0027] In addition, the base station according to the present invention is implemented in a traffic information system wherein base stations and mobile stations communicate wirelessly. Moreover, the base station according to the present invention, in the following manner, modulates signals and wirelessly transmits same to the mobile stations, and also wirelessly receives from the mobile stations a signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, and establishes synchronization from said received signal and demodulates said received signal. To wit, in the base station, an antenna transmits and receives wireless signals, a modulating means modulates signals, a transmission means wirelessly transmits modulated signals to the mobile stations via the antenna, while a receiving means receives via the antenna signals transmitted wirelessly from the mobile stations, a positive/negative change timing detection means detects the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, a synchronization establishment means establishes synchronization from said received signal based on the detected timing, and a demodulation means demodulates said received signal according to the established synchronization timing. In addition, a control means communicates the signals exchanged with the mobile station to external apparatus (e.g., other base stations or a main control facility).

[0028] The above and other objects, features and advantages of the present invention will become apparent from the description given hereinbelow with reference to the accompanying drawings.

BRIEF EXPLANATION OF THE DRAWINGS

[0029]FIG. 1 is a schematic diagram of an example of the constitution of a synchronization establishment circuit according to Example 1 of the present invention.

[0030]FIG. 2 is a diagram of one example of the constellation of the preamble pattern.

[0031]FIG. 3 is a diagram of one example of an amplitude change waveform in the preamble pattern.

[0032]FIG. 4 is a diagram of the specific constitution of a synchronization establishment circuit according to Example 1 of the present invention.

[0033]FIG. 5 is a diagram showing one example of the waveform of a squared amplitude change waveform.

[0034]FIG. 6 is a diagram showing one example of the amplitude difference based on the squared value.

[0035]FIG. 7 is a diagram showing one example of the amplitude difference based on the squared value output from a low pass filter.

[0036]FIG. 8 is a schematic diagram of an example of the constitution of a transceiver modem according to Example 2 of the present invention.

[0037]FIG. 9 is a schematic diagram of an example of the constitution of the Advanced Cruise-Assist Highway System according to Example 2 of the present invention, along with an example of the constitution of burst signals.

[0038]FIG. 10 is a diagram showing an example of the constitution of a base station provided for the Advanced Cruise-Assist Highway System.

[0039]FIG. 11 is a diagram showing an example of the constitution of a burst signal.

[0040]FIG. 12 is a diagram showing an example of the constitution of a demodulation circuit according to a prior-art example.

[0041]FIG. 13 is a diagram used to explain the problem in the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] We shall now describe the synchronization establishment circuit (synchronization establishment apparatus) according to Example 1 of the present invention with reference to drawings. Note that in this Example, we shall also describe the demodulation method according to the present invention.

[0043]FIG. 1 is a schematic diagram of an example of the constitution of a synchronization establishment circuit according to this Example. This synchronization establishment circuit is equipped with a wireless receiver that receives burst signals having the same structure as that shown in FIG. 11 above, and establishes the clock synchronization based on the preamble pattern contained in said burst signals.

[0044] In addition, this Example illustrates the case wherein the wireless transmitter and wireless receiver perform the wireless communication of signals using the π/4-shift QPSK modulation scheme. In addition, it illustrates the case in which the preamble pattern contained at the start of the burst signal wirelessly transmitted from the wireless transmitter is a pattern wherein “1001” is repeatedly generated to form the pattern “10011001100 . . . ”

[0045] Here, the pattern with “1001” repeated in π/4-shift QPSK becomes a pattern wherein the change in amplitude periodically alternates between positive and negative, and we shall now describe this is detail.

[0046]FIG. 2 shows an example of the transition in the phase and amplitude (constellation) of the modulated wave in a modulated wave generated by modulating the aforementioned preamble pattern by means of the π/4-shift QPSK modulation scheme. In the graph, the I component is shown on the horizontal axis while the Q component is on the vertical axis. Note that this modulated wave is obtained by subjecting the aforementioned preamble pattern to Gray encoding, summation logic-value conversion, and π/4-shift QPSK modulation.

[0047] As shown in this graph, in π/4-shift QPSK, the bit pattern (symbol) “10” may correspond to a phase change of −(π/4) (a phase change in which the change in phase is negative), for example, and the bit pattern (symbol) “01” may correspond to a phase change of +(3π/4) (a phase change in which the change in phase is positive), for example In addition, with a bit pattern (symbol) of “10,” the value of the amplitude is high, but with a bit pattern (symbol) of “01,” the value of the amplitude is low. To wit, in a pattern wherein “10” and “01” are repeated (a pattern wherein “1001” is repeated), the change in amplitude periodically alternates between positive and negative. In addition, with this pattern, when eight transitions in the phase of the modulated wave occur, the phase in question has undergone a transition of one complete revolution (2π), and returned to the original phase position.

[0048] Note that in this Example, the preamble pattern consists of a 1-byte ramp (R) and a 4-byte preamble, giving a total of 5 bytes of data (20 symbols worth of data), so “1001” is repeated 10 times.

[0049] In addition, while the Examples in this Specification illustrate cases wherein a pattern in which “1001” is repeated is used as the preamble pattern, according to the present invention, it is also possible to use as the preamble pattern any other pattern, as tong as the change in amplitude periodically alternates between positive and negative.

[0050] In addition, FIG. 3 illustrates one example of a waveform wherein the modulated wave of the preamble pattern shown in FIG. 2 above is sampled (digitized) by an A/D converter. In this graph, time (e.g., the value in the case that the sample number is used as a unit) is shown on the horizontal axis while the signal value of this waveform is on the vertical axis. In addition, an envelope R of this waveform is also shown in FIG. 3 As shown in FIG. 3 above, in π/4-shift QPSK, the “1001100001 . . . ” preamble pattern gives rise to a periodic change in amplitude, and the change in amplitude also periodically alternates between positive and negative In this Example, as to be described later, the detection of such a change in amplitude (direction) is used to detect the precise point of change between symbols (here, the symbol “10” and the symbol “01”) and therefore establish clock synchronization.

[0051] In reference to FIG. 1 above, we shall present a schematic example of the operation of the synchronization establishment circuit of this Example.

[0052] As shown in this figure, the synchronization establishment circuit of this Example consists of an A/D converter 1, amplitude change detection circuit 2, amplitude polarity change point detection circuit 3, change point statistical processing circuit 4 and a clock synchronization setting circuit 5.

[0053] The A/D converter I has the functions of accepting input of a burst signal (here, the preamble pattern signal contained in said burst signal) that is received as input to the demodulator, converting this signal from an analog signal to a digital signal, and providing output of the converted digital signal (digital value) to the amplitude change detection circuit 2.

[0054] The amplitude change detection circuit 2 has the functions of detecting the change in amplitude of the digital signal based on the value of the digital signal input from the A/D converter 1, and providing the results of this detection as output to the amplitude polarity change point detection circuit 3.

[0055] The amplitude polarity change point detection circuit 3 has the functions of determining the polarity of the change in amplitude (whether this change is positive or negative) detected by the amplitude change detection circuit 2, detecting the point in time (timing) when this polarity changes, and providing the results of this detection as output to the change point statistical processing circuit 4. Note that such a polarity change point may be acquired by detecting the timing at which the polarity of the amplitude change detected by the amplitude change detection circuit 2 inverts (changes from positive to negative, or changes from negative to positive), and namely, this timing can be used as the polarity change point.

[0056] The change point statistical processing circuit 4 has the functions of counting the number of polarity change points detected by the amplitude polarity change point detection circuit 3 within the measurable range of the preamble pattern, for example, and also determining the timing period (time interval between adjacent polarity change points) that most closely fits the detected plurality of polarity change points, and providing output of the results of this determination to the clock synchronization setting circuit 5.

[0057] Note that assuming no errors in wireless communications, it would be possible to detect one timing period for every symbol, but considering the errors in actual wireless communications, it is preferable to sample a large number of timing periods (preferably as many as possible). In addition, the number of samplings of the timing period may be determined based on the length (period) of the preamble pattern, for example. The aforementioned change point statistical processing circuit 4 tabulates the sampled timing periods, and, for example, may take an average of a plurality of detected results and report the resulting timing period to the clock synchronization setting circuit 5, or, determine the most frequently detected timing period based on a distribution of the tabulated results and report this to the clock synchronization setting circuit 5.

[0058] The clock synchronization setting circuit 5 has the functions of using the timing period reported from the change point statistical processing circuit 4 to establish the clock synchronization (bit synchronization), and providing output of a synchronization clock generated based thereupon to the various processors (that operate on this synchronization clock). Note that the establishment of clock synchronization is achieved by matching the period of the pulse signals that constitute this clock to the aforementioned timing period.

[0059] Next, we shall present an example of a more specific constitution of the synchronization establishment circuit of this Example, and an example of its operation.

[0060]FIG. 4 shows a more specific constitution of the synchronization establishment circuit of this Example.

[0061] The synchronization establishment circuit shown in this diagram consists of an amplitude difference detection circuit T1, low pass filter 15, polarity bit converter Z, change point extraction circuit T2, change point measurement circuit T3, clock synchronization circuit T4 and a timing generation circuit T5.

[0062] Note that in the circuit of this Example, analog data is sampled at a clock running at 16 times the baud rate.

[0063] The amplitude difference detection circuit T1 consists of an A/D converter 11, multiplier 12, adder 13 and sixteen (sixteen stages of) registers 14 a through 14 p.

[0064] Based on a timing signal output from a timing generator 22 to be described later, for example, the A/D converter 11 accepts input of a burst signal (here, the preamble pattern signal contained in said burst signal) that is received as input to the demodulator, converts this signal from an analog signal to a digital signal (8-bit in this Example), and provides output of the converted digital signal (digital value) via two paths to the multiplier 12. Here, as one example of the waveform when the preamble pattern is sampled (digitized) by A/D converter 11 and output (the value at point “a” shown in FIG. 4), the waveform shown in FIG. 3 above results.

[0065] The multiplier 12 takes the digital signal output from the AID converter 11 that is input via two paths, multiplies these two digital signals (digital values) and outputs the result of this multiplication the adder 13 and the first-stage register 14 a. Here, the multiplication result output from the multiplier 12 becomes the square of the value of the digital signal (digital value) output from the A/D converter 11.

[0066] In addition, FIG. 5 illustrates one example of the waveform of the signal output from the multiplier 12 (the value at point “b” shown in FIG. 4), namely the waveform of the square of the output waveform from A/D converter 11 (the waveform shown in FIG. 3 above). In the graph, the time is shown on the horizontal axis while the squared value is on the vertical axis. Referring to the waveform in the graph (the squared value), one can see the temporal change in the amplitude of the received signal. To wit, a large squared value is equivalent to a high amplitude value, and a small squared value is equivalent to a low amplitude value.

[0067] Based on a timing signal output from a timing generator 22 to be described later, for example, the first-stage register 14 a outputs the squared value input from the multiplier 12 to the next-stage register 14 b after a delay of one clock cycle (of the aforementioned clock running at 16 times the baud rate).

[0068] Similarly, based on a timing signal output from a timing generator 22 to be described later, each of the second- through fifteenth-stage resisters 14 b-14 o outputs the squared value input from the previous-stage register to the next-stage register after a delay of one clock cycle.

[0069] Based on a timing signal output from a timing generator 22 to be described later, for example, the sixteenth-stage (last-stage) register 14 p inputs the squared value input from the previous-stage register 14 o and outputs it to adder 13 after a delay of one clock cycle.

[0070] By each of these sixteen registers 14 a-14 p delaying the squared value by one clock cycle, the squared value is delayed by a total of 16 clock cycles (1 symbol) and output to the adder 13.

[0071] Adder (in this Example, a device that adds with positive and negative inverted) 13 accepts input of the squared-value data (taken to be X1 here) input from the multiplier 12 and also accepts input of this squared-value data shifted by sixteen clock cycles (taken to be X2 here) from register 14 p and outputs the difference between these two pieces of data (in this example, X1-X2) to the low pass filter 15.

[0072] In addition, FIG. 6 shows the waveform of the difference signal output from the adder 13 (the value at point “c” shown in FIG. 4). In the graph, the time is shown on the horizontal axis while the temporal change in the squared value (amplitude difference based on the squared value) is on the vertical axis.

[0073] The low pass filter 15 filters the difference signal input from the adder 13, thereby eliminating noise from the difference signal, and outputs this signal difference to the polarity bit converter Z.

[0074] Here, FIG. 7 shows the waveform of the difference signal (after filtering) output from the low pass filter 15 (the value at point “d” shown in FIG. 4). In the graph, the time is shown on the horizontal axis while the temporal change in the squared value (amplitude difference based on the squared value) is on the vertical axis.

[0075] As shown in FIG. 7 above, the waveform of the aforementioned difference signal becomes a waveform wherein positive values and negative values alternate (e.g., a sine wave shape), and the points where the values in this waveform (values on the vertical axis) cross zero (0) (points where values change from positive to negative or points where values change from negative to positive) appear at time intervals (intervals on the horizontal axis) equal to the period of the baud rate.

[0076] The polarity bit converter Z outputs data with a value of “1” to register 16 and XOR 17 provided in the change point extraction circuit T2 if the polarity of the value input from the low pass filter 15 is positive, but outputs data with a value of “0” to register 16 and XOR 17 if the polarity is negative.

[0077] The change point extraction circuit T2 consists of a register 16 and XOR 17.

[0078] Based on the timing signal output from the timing generator 22 to be described later, for example, the register 16 shifts (e.g., delays) the value of the data input from polarity bit converter Z by one clock cycle and outputs the result to XOR 17.

[0079] In the case that the values of data input from the polarity bit converter Z and register 16 are different, the XOR 17 provides output to a serial/parallel converter 18 provided in the change point measurement circuit T3 data of the value “1,” or provides output to the serial/parallel converter 18 of data of the value “0” in the case that the values of data input from the polarity bit converter Z and register 16 are the same (namely the positive or negative polarity of the data value is unchanged).

[0080] By means of such a constitution and operation, the change point extraction circuit T2 is able to extract the timing (positive/negative change points) at which the value of the waveform of the amplitude difference based on the squared value crosses the zero (0) point To wit, specifically, for the waveform of the amplitude difference based on the squared value, it is possible to compare the polarity (positive/negative) of data not shifted by 1 clock cycle against the polarity (positive/negative) of data shifted by 1 clock cycle, and thus detect the points of the timing at which these two polarities are different (points at which the polarity changes) as the positive/negative change points of the amplitude difference.

[0081] The change point measurement circuit T3 consists of a serial/parallel converter 18, adder 19, and a register 20.

[0082] The serial/parallel converter 18 converts data input from the XOR 17 from serial data to parallel data, and outputs this data (in this Example, data that represents the time interval between adjacent values of “1”) to the adder 19.

[0083] The adder 19 cumulatively adds the values of data input from the serial/parallel converter 18 a total of 16 times (16 clock cycles), and outputs the result of addition to the register 20.

[0084] Based on a timing signal output from a timing generator 22 to be described later, for example, the register 20 shifts the result of addition (a binary value) input from the adder 19 by 4 bits (in the direction of the smaller places) and outputs this shifted result of addition (average value) to a synchronizer 21 provided in the clock synchronization circuit T4. Note that when the 4-bit shift described here is performed, the result of addition is divided by 16, and thus, the result of addition of the 16 values is divided by 16 to give an average value.

[0085] By means of such a constitution and operation, the change point measurement circuit T3 counts and cumulatively adds 16 values of the timing (in this Example, data that represents the time interval between adjacent values of “1”) of the positive/negative change points of the measured phase difference, and then performs a 4-bit shift of the binary value of the result of addition and thus obtains an average value.

[0086] Note that the number of values of the change point timing (number of samplings) used when obtaining the average value of the positive/negative change point timing of the phase difference may be various, and as one example, it is preferable to use the average value of eight values of the change point timing near the center of the 20 symbols constituting the preamble pattern where it is (assumed to be) stable.

[0087] The clock synchronization circuit T4 is provided with a synchronizer 21 Based on the timing signal input from the timing generator 22 to be described later, for example, and the average value (of the positive/negative change point timing of the amplitude difference) input from the register 20, the synchronizer 21 establishes the clock timing and outputs a base (synchronization) clock signal according to the synchronization timing thus established.

[0088] Note that specifically, in the synchronizer 21, the clock is reset based on the timing signal input from the timing generator 22 and also, the clock is reset at each time interval corresponding to the average value (of the positive/negative change point timing of the amplitude difference) input from the register 20, and thus the synchronization of the clock can be established. In this manner, by using average values from a plurality of samplings of the time intervals at which positive/negative change points in the amplitude difference are detected, it is possible to establish the clock synchronization.

[0089] The timing generation circuit T5 is provided with a timing generator 22.

[0090] Based on the timing signal input from the timing generator 22 to be described later, for example, the timing generator 22 generates a timing signal that determines the position when the clock is reset (position of the start of synchronization), and outputs this timing signal to the synchronizer 21 and the like.

[0091] As described above, in the synchronization establishment circuit of this Example, at the time that a (received) burst signal modulated by means of the :/4-shift QPSK modulation scheme is demodulated by means of the 7/4-shift QPSK demodulation scheme, the temporal amplitude difference (amplitude change) of the preamble pattern is detected, the detected amplitude difference is set as an offset level, the polarity of the amplitude difference as the offset level is detected, and a base clock signal is generated based on the time intervals at which the detected points of change of polarity occur.

[0092] In addition, at this time, in the synchronization establishment circuit of this Example, taking advantage of the fact that the amplitude difference (amplitude change) of the preamble pattern periodically alternates between positive and negative, specifically, the polarity of this phase difference is detected and also the timing at which this polarity changes between positive and negative is detected, and by resetting the clock based on the result of calculating the average value of the time interval at which the this polarity changes between positive and negative, clock synchronization is established.

[0093] Moreover, in a demodulation circuit equipped with such a synchronization establishment circuit according to this Example, it is possible to demodulate accurately the unique word and data contained in a received burst signal according to the base clock signal generated by the synchronization establishment circuit according to this Example.

[0094] Accordingly, in the synchronization establishment circuit of this Example, by establishing the clock synchronization based on the timing at which the amplitude difference of the preamble pattern periodically alternates between positive and negative, it is possible to establish synchronization in a short period of time. Thereby, it is possible to make the length (period) of the preamble pattern relatively short and increase the data transmission rate. In addition, even when a preamble pattern of a short length (period) is used, synchronization is established within the period of the preamble pattern, so it is possible for the received data in the first burst reception to be received correctly and reliably.

[0095] Note that in the synchronization establishment circuit of this Example, the carrier signal is not generated autonomously, for example, but rather the relative amplitudes of the preamble pattern contained in the (received) burst signal are used to establish synchronization. In this case, in the synchronization establishment circuit of this Example, the amplitude difference is processed as a periodic waveform and also, the positive or negative polarity of the value of this waveform is determined to detect the positive/negative change point timing of the amplitude difference, and the synchronization is established based on the results of this detection.

[0096] In a demodulation circuit equipped with the synchronization establishment circuit of this Example, at the time that demodulation is performed as described above, for example, it is also possible to establish synchronization from a plurality of (received) burst signals for each burst signal, and demodulate each burst signal according to the synchronization timing thus established (for each burst signal).

[0097] In this case, with the synchronization establishment circuit of this Example, synchronization can be established in a short period of time, so even in the case in which a plurality of (received) burst signals containing preamble patterns as in this Example are received at nearly the same timing, it is possible to establish synchronization with each of this plurality of burst signals in a short period of time, and thus it is possible to establish synchronization in a short period of time with the entire plurality of burst signals.

[0098] Here, in this Example, the preamble pattern in which “1001” repeats is equivalent to the “synchronization establishment signal wherein the change of the amplitude periodically alternates between positive and negative” referred to in the present invention, and the received burst signal containing this preamble pattern is equivalent to the “received signal containing a synchronization establishment signal” referred to in the present invention.

[0099] In addition, in this Example, the change point extraction circuit T5 shown in FIG. 4 above has the function of detecting the timing at which the change in amplitude of the preamble pattern contained in the received burst signal changes between positive and negative, and constitutes the “positive/negative change timing detection means” referred to in the present invention. Note that while the direction of change of the amplitude (in the positive direction or negative direction) was detected based on the squared waveform of the preamble pattern in this Example, it is also possible to detect whether the amplitude changes in the positive direction or the negative direction even if the squaring process is not performed, for example.

[0100] In addition, in this Example, the clock synchronization circuit T4 shown in FIG. 4 above has the function of establishing clock synchronization from the received burst signals based on the detected timing, and constitutes the “synchronization establishment means” referred to in the present invention.

[0101] Next, we shall describe a transceiver modem (modem) as Example 2 of the present invention with reference to FIG. 8. Note that the transceiver modem according to this Example is mounted within wireless communications equipment that performs wireless communications using the π/4-shift QPSK modulation/demodulation scheme, being provided between an antenna that transmits and receives wireless signals and the controller that controls the various signals thus transmitted and received, thereby connecting said antenna and said controller.

[0102]FIG. 8 is a schematic diagram of an example of the constitution of a transceiver modem according to this Example. This transceiver modem consists of an A/D converter 31, demodulator 32, two filters 33 and 34, a detector 35, parallel/serial converter 36, clock phase detection circuit 37, and a synchronization establishment circuit 38 as the circuits on the receiving side, and also consists of a modulator 39 and a filter 40 as the circuits on the transmitting side.

[0103] We shall first describe the circuits on the receiving side.

[0104] The A/D converter 31) converts signals received via the antenna from analog signals to digital signals, and outputs the converted received signal to the demodulator 3 2 and synchronization establishment circuit 3 )8.

[0105] The synchronization establishment circuit 38 may be constituted with the same circuit constitution as that shown in FIG. 4 above, for example, and establishes clock synchronization based on received signals (e.g., the same preamble pattern as that illustrated in Example 1 above) input from the A/D converter 31, and outputs a base clock signal generated thereupon to a detector 35 to be described later.

[0106] The demodulator 32 demodulates the I component and Q component of the received signal input from the A/D converter 31, and outputs this I component to one of the filters 3 and outputs this Q component to the other of the filters 34.

[0107] The one filter 3 takes the I component input from the demodulator 32, filters it and outputs it to the detector 3)5.

[0108] The other filter 34 takes the Q component input from the demodulator 32, filters it and outputs it to the detector 35.

[0109] The detector 35 performs delayed detecting based on the base clock signaling from the synchronization establishment circuit 38. Specifically, the I and Q components input from the two filters 33 and 34 are detected (demodulated) and the demodulated data (2-bit) thus obtained is output to the parallel/serial converter 3 6.

[0110] The parallel/serial converter 3)6 converts demodulated data input from the detector 35 from parallel data to serial data and outputs same to the controller.

[0111] Note that the clock phase detection circuit 37 detects the phase of the clock and supplies the results of detection as output to the AID converter 31, the two filters 33 and 34 and the detector 35.

[0112] Next, we shall describe the circuits on the transmitting side

[0113] The modulator 39 accepts input from the controller of a signal (data) to be transmitted, modulates this signal and outputs same to the filter 40.

[0114] The filter 40 filters the modulated signal input from the modulator 39 and outputs same to the antenna

[0115] In this manner, with the transceiver modem according to this Example, the receiver inputs a signal received wirelessly via the antenna, the modulator modulates this received signal and outputs it to the controller. On the other hand, at the time that the modulator modulates the signal input from the controller and the transmitter wirelessly transmits this modulated signal via the antenna, the received signal is demodulated by a demodulation circuit equipped with a synchronization establishment circuit 3)8 such as that illustrated in Example 1 above, for example. Thus, with the transceiver modem according to this Example, it is possible to obtain effects such as being able to establish synchronization in a short period of time, in the same manner as that described in relation to the synchronization establishment circuit illustrated in Example 1 above, for example.

[0116] Here, the “modulation means” referred to in the present invention is constituted in this Example by the function of the modulator 39 modulating the transmitted signal (data subject to transmission).

[0117] In addition, the “positive/negative change timing detection means” and “synchronization establishment means” referred to in the present invention are constituted in this Example by the functions of the synchronization establishment circuit 38 detecting the timing at which the positive/negative polarity of the change in amplitude changes in the preamble pattern contained in the received burst signal, and establishing clock synchronization from this received burst signal based on the detected timing.

[0118] In addition, the “demodulation means” referred to in the present invention is constituted in this Example by the function of the detector 35 demodulating the (unique word and data contained in the) received burst signal according to the synchronization timing established by the synchronization establishment circuit 38.

[0119] Next, we shall describe a base station used in the Advanced Cruise-Assist Highway System (AHS) as Example 3 of the present invention, with reference to drawings. Note that the Advanced Cruise-Assist Highway System in this Example is one example of the “traffic information system” referred to in the present invention.

[0120]FIG. 9(a) is a schematic diagram of an example of the constitution of the Advanced Cruise-Assist Highway System according to this Example. This system consists of a plurality of base stations 41 installed (in a fixed manner, for example) in the vicinity of roads 44, and a plurality of mobile stations (wireless equipment installed in automobiles or other mobile equipment, for example) 42 that move along the roads 44. Note that FIG. 9(a) includes symbols (“44,” “41,” “42”) for only a portion of the roads, one base station and one mobile station, and the symbols are omitted for the others. In addition, the cell 43 of base station 41 which is given a symbol is illustrated as an example.

[0121] In the Advanced Cruise-Assist Highway System illustrated in FIG. 9(a), one base station 41 uses the π/4-shift QPSK modulation/demodulation scheme, for example, to wirelessly communicate traffic-related information or the like to a plurality (a maximum of 12 in this Example) of mobile stations 42 present within its cell.

[0122] In addition, in the Advanced Cruise-Assist Highway System of this Example, when wireless communications are performed using a burst signal containing a preamble pattern like that illustrated in Example 1 above, for example, the frame format of the burst signal used in communications from the base station 41 of this Example to the mobile stations 42 may have, as shown in FIG. 9(b) for example, twelve slots D1 through D12 in the data portion, and thus, it is possible for one base station 41 to communicate wirelessly with a maximum of twelve mobile stations 42 (simultaneously).

[0123]FIG. 10 is a diagram showing an example of the constitution of the aforementioned base station. This base station 41 consists of an antenna 51, receiver 52, demodulator 53, modulator 54, transmitter 55, and a controller 56.

[0124] The antenna 51 receives wireless signals.

[0125] Via the antenna 51, the receiver 52 receives signals transmitted wirelessly from the mobile stations 42, and provides output of these received signals to the demodulator 53.

[0126] The demodulator 53 has a synchronization establishment circuit like that illustrated in FIG. 4 above and also has a circuit for demodulating the received signals. It establishes clock synchronization based on the received signals (e.g., a preamble pattern like that illustrated in Example 1 above) input from the receiver 52 and also modulates the received signals based on the synchronization clock thus established and provides output of the results of this demodulation to the controller 56.

[0127] The modulator 54 accepts input from the controller 56 of signals (data) to be transmitted, modulates these signals and outputs same to the transmitter 55.

[0128] The transmitter 55 uses the antenna 51 to transmit modulated signals input from the modulator 54 wirelessly to the mobile stations 42.

[0129] The controller 56 may be connected to other apparatus (e.g., other base stations or a main control facility) by wire, for example, and may transmit signals (demodulated data) input from the demodulator 53 to this other apparatus, or may receive signals (data) transmitted from this other apparatus and output same to the modulator 54, thereby performing the exchange of sent/received signals with this other facility.

[0130] As described above, with the base station 41 of this Example, when the receiver 52 accepts input of signals wirelessly received via the antenna 51, modulates these received signals and outputs them to the controller 56, or when the modulator 54 modulates signals input from the controller 56 and the transmitter 55 wirelessly transmits these modulated signals from the antenna 51, a demodulator 53 provided with a synchronization establishment circuit like that illustrated in Example 1 above is used to demodulate the received signals. For this reason, with the base station 41 of this Example, in the same manner as described with regard to the synchronization establishment circuit illustrated in Example 1 above, synchronization can be established in a short period of time and other meritorious effects can be obtained.

[0131] As one example, with the base station 41 of this Example, even in the case in which a plurality of mobile stations 42 enter the cell 43 at high speed and synchronization must be established quickly with each of the mobile stations 42, it is possible to establish this synchronization in a short period of time as described in Example 1 above, so communication with each of the mobile stations 42 is possible.

[0132] Note that in the prior-art synchronization detection scheme, while transmitting and receiving between one base station and one mobile station (namely one-to-one transmitting and receiving) is possible, in the case in which a plurality of mobile stations enter the cell at high speed as described above, a problem arose wherein the mobile stations would leave the cell before the base station had established synchronization. In addition, with PHS, for example, because of the synchronization detection scheme adopted therein (a scheme wherein synchronization is established gradually while performing feedback of the signal subject to synchronization), communication between one base station and a plurality of mobile stations is performed, but with PHS, in order to establish communication between a base station and a high-speed mobile station, simultaneous transmission and reception with a different base station is utilized. To wit, with PHS, a single base station cannot establish synchronization quickly. The base station 41 of this Example can solve this problem with the prior art.

[0133] Here, in the base station 41 of this Example, the antenna 51 that transmits and receives wireless signals is equivalent to the “antenna” referred to in the present invention.

[0134] In addition, in the base station 41 of this Example, the signal modulating function of the modulator 54 constitutes the “modulation means” referred to in the present invention.

[0135] In addition, in the base station 41 of this Example, the function whereby the transmitter 55 wirelessly transmits modulated signals to the mobile stations 42 via antenna 51 constitutes the “transmission means” referred to in the present invention.

[0136] In addition, in the base station 41 of this Example, the function whereby the receiver 52 receives wirelessly transmitted signals from the mobile stations 42 via antenna 51 constitutes the “receiving means” referred to in the present invention.

[0137] In addition, in the base station 41 of this Example, the function whereby the demodulator 53 detects the timing of the positive/negative polarity change in the change in amplitude of the preamble pattern contained in the received burst signal, and establishes clock synchronization from said received burst signal based on the detected timing and the function whereby the (unique word and data contained in the) received burst signal is demodulated according to the established synchronization timing constitute the “positive/negative change timing detection means,” “synchronization establishment means” and “demodulation means” referred to in the present invention.

[0138] In addition, in the base station 41 of this Example, the function whereby the controller 56 communicates the signals exchanged with the mobile stations 42 to external apparatus constitutes the control means referred to in the present invention.

[0139] Here, the embodiment of the demodulation method according to the present invention, and the constitution of the synchronization establishment apparatus, modem or traffic information system according to the present invention are in no way limited to those illustrated above, but rather various embodiments or constitutions may be used In addition, the applicable fields of the present invention are in no way limited to those illustrated above, but rather the present invention is applicable to various fields.

[0140] In addition, the above describes the demodulation method and apparatus of the side that establishes synchronization based on a synchronization establishment signal (the receiving side), but the modulation method and apparatus of the side that transmits such a synchronization establishment signal is to have a constitution whereby it generates a signal that contains a synchronization establishment signal (e.g., a preamble pattern such as that illustrated in Example 1 above) wherein the change in amplitude periodically alternates between positive and negative (e.g., a burst signal modulated by the π/4-shift QPSK modulation scheme) and transmits same to the receiving side.

[0141] In addition, the synchronization establishment processing and various types of processing performed by the method and apparatus according to the present invention may be constituted by being implemented in hardware resources equipped with a processor and memory and the like, for example, being controlled by means of a processor executing a control program stored in ROM. In addition, the various functional means for executing this processing may also be constituted as independent hardware circuits.

[0142] In addition, the present invention may also be understood as one wherein the above control program is stored in a floppy disk, CD-ROM or other computer-readable recording media, so that the processing according to the present invention can be implemented by loading said control program from the recording medium into a computer and executing the program by a processor.

[0143] As described above, with the demodulation method, synchronization establishment apparatus, modem and base station according to the present invention, the synchronization is established from a received signal based on the timing of a change in the positive/negative polarity of the change in amplitude of a synchronization establishment signal contained in a received signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, so synchronization can be established in a short period of time and other meritorious effects can be obtained. 

What is claimed is:
 1. A demodulation method for establishing synchronization from a received signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, and demodulating said received signal, the demodulation method comprising a step of establishing synchronization from said received signal based on the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, and demodulating said received signal.
 2. A demodulation method according to claim 1, wherein synchronization is established from a plurality of received signals for each received signal and each of said received signals is demodulated.
 3. A synchronization establishment apparatus that establishes synchronization from a received signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, the synchronization establishment apparatus comprising: positive/negative change timing detection means that detects the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, and synchronization establishment means that establishes synchronization from said received signal based on the detected timing.
 4. A modem that modulates transmitted signals, and also establishes synchronization from a received signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, demodulates said received signal the modem comprising: modulating means that modulates transmitted signals, positive/negative change timing detection means that detects the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, synchronization establishment means that establishes synchronization from said received signal based on the detected timing, and demodulation means that demodulates said received signal according to the established synchronization timing.
 5. In a traffic information system wherein base stations and mobile stations communicate wirelessly, a base station that modulates signals and wirelessly transmits same to the mobile stations, and also wirelessly receives from the mobile stations a signal that contains a synchronization establishment signal wherein the change in amplitude periodically alternates between positive and negative, establishes synchronization from said received signal and demodulates said received signal the base station comprising: an antenna that transmits and receives wireless signals, modulating means that modulates signals, transmission means that wirelessly transmits modulated signals to the mobile stations via the antenna, receiving means that receives via the antenna signals transmitted wirelessly from the mobile stations, positive/negative change timing detection means that detects the timing of changes in the positive/negative polarity of the change in amplitude of the synchronization establishment signal contained in the received signal, synchronization establishment means that establishes synchronization from said received signal based on the detected timing, demodulation means that demodulates said received signal according to the established synchronization timing, and control means that communicates the signals exchanged with the mobile station to external apparatus.
 6. A synchronization establishment apparatus according to claim 3, wherein synchronization is established from a plurality of received signals for each received signal.
 7. A modem according to claim 4, wherein synchronization is established from a plurality of received signals for each received signal and each of said received signals is demodulated.
 8. A base station according to claim 5, wherein synchronization is established from a plurality of received signals for each received signal and each of said received signals is demodulated.
 9. A demodulation method according to claim 1, wherein a preamble pattern wherein 1001 is repeated in π/4-shift QPSK is used as the synchronization establishment signal, and a burst signal containing said preamble pattern is used as the received signal.
 10. A synchronization establishment apparatus according to claim 3, wherein a preamble pattern wherein 1001 is repeated in π/4-shift QPSK is used as the synchronization establishment signal, and a burst signal containing said preamble pattern is used as the received signal.
 11. A modem according to claim 4, wherein a preamble pattern wherein 1001 is repeated in π/4-shift QPSK is used as the synchronization establishment signal, and a burst signal containing said preamble pattern is used as the received signal.
 12. A base station according to claim 5, wherein a preamble pattern wherein 1001 is repeated in π/4-shift QPSK is used as the synchronization establishment signal, and a burst signal containing said preamble pattern is used as the received signal.
 13. A synchronization establishment apparatus according to claim 10, wherein the synchronization establishment apparatus comprises: an amplitude difference detection circuit that uses an A/D converter to convert the received burst signal from an analog signal to a digital signal, squares the value of the converted digital signal, and outputs the temporal change of said squared value as a difference signal, a low pass filter that takes the difference signal from the amplitude difference detection circuit, and filters and outputs the signal, a polarity bit converter that outputs data of different values when the polarity of the output value from the low pass filter is positive than when negative, a change point extraction circuit that, based on the output value from the polarity bit converter, extracts the timing at which the value of the waveform of the amplitude difference based on the squared value crosses the zero point, a change point measurement circuit that averages the positive/negative change point timing of said extracted amplitude difference based on the squared value, a clock synchronization establishment circuit that, based on the average value from the change point measurement circuit, establishes clock synchronization, and a timing generation circuit that, based on the timing at which the received burst signal starts, determines the position to reset the clock. 